This invention relates to a method for laying out the power bus routing in an integrated circuit chip including intermixed fixed size and shape rectangular macrocells together with amorphous clusters of standard cells.
Modern integrated circuit technology is widely used for communications and control. Because of the advantages of reliability and operating speed, the complexity of integrated circuit chips has increased with time, notwithstanding the disadvantages of lower yields occasioned by such complex chips. At the current state of technology, up to one million transistors may be used on a single large-scale integrated circuit.
While such large integrated circuits are advantageous, the initial layout of such complex devices, and of the interconnections between the transistors presents problems in the length of time required to accomplish the layout of the interconnections, the total man-hours required, and in the high skill required of the layout personnel. Furthermore, human layout is subject to the problem of errors, and also is undesirably dependent upon human intuition, rather than upon rote evaluation of all possible permutations of the layout. Thus, layout by humans may not be optimum in terms of the chip size and operating speed of the resulting integrated circuit. The larger chip size resulting from human layout, in turn, results in lower yields during the manufacture of the integrated circuit, which increases the cost.
As a result of the limitations of human layout, it has become common to lay out the integrated circuits including the transistors and their interconnections by means of computer-aided design. These computerized layout systems accept as inputs an interconnection list between the logic elements. In this context, logic elements are relatively primitive electrical circuit such as AND gates, OR gates, and the like. Such logic elements are often standard cells having a fixed dimension and a variable dimension to aid in their placement. Other inputs to the computer layout program include the physical sizes associated with the standard cells, and the locations of the connection points (pins) around the peripheries of the standard cells.
Various methods have been devised for operating on this information to produce the desired layout. One method is described in U.S. Pat. No. 4,593,363 issued June 3, 1986 to Burstein et al. This method operates only with standard cells. This has the disadvantage that LSI layouts including macrocells cannot be conveniently handled except by the intervention of human layout experts. Macrocells, on the other hand, are relatively sophisticated circuits such as memories or multipliers, digital filters and the like, which have fixed dimensions, often because they were laid out by hand. In general, the structure of macrocells is regular. Another system is described in U.S. Pat. No. 4,577,276 issued Mar. 18, 1986 to Dunlop et al., which has the same disadvantages as Burstein et al.
Copending U.S. patent application Ser. No. 07/064,044, filed June 19, 1987 in the names of the inventors herein, and entitled "A Structured Design Method for High Density Standard Cell and Macrocell Layout of VLSI Chips," describes an automated chip layout system which advantageously lays out macrocells in a large scale integrated (LSI) circuit intermixed with standard logic cells. This method groups standard logic cells together in right-left or top-bottom (as viewed from the broad upper side of the chip) pairs to form low-level subdomains, and progressively combines the low-level subdomains together with standard logic cell or other low-level subdomains to produce higher-level, larger subdomains, until no advantage is achieved by further combinations. The remaining subdomains are designated as domains. Pairings of macrocells and domains are made in either top-bottom or right-left topological configurations to produce low-level superdomains, and the superdomains are paired with domains, macrocells or other superdomains to produce higher-level superdomains. This process continues until only one superdomain remains. This produces a topological layout in which domains, superdomains and macrocells are located on a rectangular grid with wiring or routing channels therebetween.
Once the layout of the logic elements and macrocells is established by any of the above methods, it is necessary to route the direct current (dc) power buses to all the elements requiring power. The dc power bus system must distribute positive (+) and negative (-), power. Often, one of the polarities is designated as ground, and the other as V.sub.DD, B+ or B-. The dc power distribution system must provide low resistance paths between the power wire bonding pads and each circuit being powered, so that the voltage drops along the power bus in response to instantaneously high switching currents are insignificant and do not affect other circuits being powered from the same bus. The dc power distribution system must not bock or obstruct the paths of the signal wiring, and should be amenable to automatic layout. Some prior art dc power bus layouts use a single metallization layer, and begin with a single large bus, which is branched repeatedly to attempt to reach each and every element to be powered. However, because of the inability to cross one conductor over another, it is not possible to guarantee that all circuits can be powered. Also, the branching structure of the buses causes high currents to flow in some portions, and may result in high resistance and undesired circuit interaction. The single metal layer power bus structure tends to obstruct the signal wiring.
A power bus distribution structure is desired which is amenable to automated layout, tends to minimize the power bus resistance, and guarantees powering of all circuits.